1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device in which a sense amplifier compares a sense potential generated from a memory cell, with a reference potential generated from a reference cell having the same structure as the memory cell to sense data, and more particularly to a semiconductor memory device having a reference cell transistor for generating the reference potential whose gate voltage can be controlled in the readout and write-in operations.
2. Description of the Related Art
FIG. 1 shows the schematic construction of a conventional semiconductor memory device, for example, a conventional electrically data programmable read only memory (EPROM). In FIG. 1, memory cell MC1 (like memory cell MCn) is a stacked gate transistor. FIG. 2 is a cross sectional view showing the construction of memory cell MC1. Source 72 and drain 73 formed of n.sup.+ -type diffusion regions are formed in the surface area of p-type substrate 71, floating gate 74 is formed on that portion of the substrate which lies between the source and drain, and control gate 75 is formed on the floating gate. The film thickness of that portion of insulation film 76 which lies between substrate 71 and floating gate 74 is set to tox1 and the film thickness of that portion of insulation film 76 which lies between floating gate 74 and control gate 75 is set to tox2.
Since the EPROM is a nonvolatile memory, data programmed into memory cell MC1 can be permanently stored unless all the stored data is erased by application of ultraviolet rays. In this case, the "data programming" means that electrons are injected into floating gate 74 of memory cell MC1 and the data of the memory cell is set to "0". Memory cell MC1 having data of "1" is in the erased state. In order to program data "0" into the memory cell, write-in voltage Vpp of 12.5 V, for example, is simultaneously applied to drain 73 and control gate 75 of the memory cell, thereby causing hot electrons to be injected into the floating gate from the channel. As a result, the threshold voltage of the programmed memory cell transistor is raised and thus data is programmed into memory cell MC1 of the EPROM.
In the readout mode, voltage Vcc of 5 V, for example, is applied to control gate 75 to read out data stored in memory cell MC1.
As described above, in the EPROM, the level of a voltage applied to control gate 75 when data is programmed into memory cell MC1 is different from that applied when data is read out from the memory cell. Voltage Vcc (5 V) is applied in the data readout operation, and voltage Vpp (12.5 V) is applied in the data programming operation. Therefore, it is necessary to provide a switching circuit for internal power source which supplies voltages Vcc and Vpp in accordance with the internal state in addition to externally supplied power source voltages Vcc (5 V) and Vpp (12.5 V).
As shown in FIG. 1, the switching between voltages Vcc and Vpp is effected by use of voltage switching circuit 102. Switching circuit 10 is supplied with data readout voltage Vcc via terminal 142 and data programming voltage Vpp via terminal 144. The voltage Vcc or Vpp as voltage SW is selectively supplied according to an programming control signal (write enable signal). Voltage Vpp is also supplied to programming control section 104. Programming control section 104 includes transistor 134 whose drain and source are respectively connected to terminal 144 and column selection gate circuit 108 and programming control buffer 132 connected to receive voltage Vpp as a power source voltage for controlling the gate voltage of transistor 134 according to programming data Din.
Column decoder 106 decodes a column address included in the input address to output the decoded result to column selection gate circuit 108. Circuit 108 includes N-channel MOS transistors and selects bit line 120 based on the decoded result of decoder 106. Row decoder 110 decodes a row address included in the input address to output the decoded result to word in buffer 112. Buffer 112 is supplied with voltage SW from circuit 102 as the power source voltage and supplies a voltage to control gate 75 of memory cell MC1.
The source and drain of memory cell MC1 are respectively connected to ground voltage Vss and bit line 120. Bit line 120 is connected to one input terminal of sense amplifier 116 via transistors of column selection gate circuit 108. Sense amplifier 116 senses "1" or "0" of data stored in memory cell MC1 by comparing the potential of sense line 123 varying according to data stored in one of memory cells MC1 selected by row decoder 110 and column decoder 106 with a reference potential on line 124 to be described later.
Reference voltage generation circuit 122 supplies a reference voltage to sense amplifier 116. Circuit 122 includes reference cell DC constructed by the same stacked gate transistor as memory cell MC1 and that is in the erased state normally turned-on transistors 114 of the same number as the transistors series-connected in column selection gate circuit 108. The gate of reference cell DC is supplied with power source voltage Vcc. The level of the reference voltage is determined by turning on reference cell DC. In order to obtain a stable reference potential, it is necessary to design the transistor characteristics of memory cell MC1 and reference cell DC equal to each other.
With the above construction, when data is programmed into memory cell MC1, programming voltage Vpp is supplied as voltage SW from power source switching circuit 102 to word line buffer circuit 112. At the same time, programming voltage Vpp is supplied from programming controlling buffer 12 to the gate of programming controlling transistor 134. If the threshold voltage of transistor 134 is Vth, a voltage of (Vpp-Vth) is supplied to the drain of memory cell MC1 via column selection gate circuit 108. Word line buffer 112 supplies programming voltage Vpp to the control gate of memory cell MC1. As a result, hot electrons are injected into floating gate 74 to raise the threshold voltage of memory cell MC1. In this way, data is programmed into memory cell MC1.
When data is read out from memory cell MC1, voltage Vcc is supplied as voltage SW from power source switching circuit 102 to word line buffer 112. At this time, voltage Vcc is supplied from word line buffer 112 to the control gate of memory cell MC1. A voltage corresponding to data stored in memory cell MC1 to be supplied to sense amplifier 116 via column selection gate circuit 108. A reference voltage is also supplied from reference voltage generating circuit 122 to sense amplifier 116. Then, sense amplifier 116 compares the voltage supplied from memory cell MC1 with that supplied from reference cell DC and outputs the comparison result as readout data to the data line.
In the conventional EPROM, if power source voltage Vcc is varied by the influence of noise, the control gate voltage of the reference cell is also varied. However, since voltage SW is coupled with voltage Vcc via the transistor of voltage switching circuit 102, variation in the control gate voltage of the memory cell will become different from that in the control gate voltage of the reference cell. As a result, the characteristics of the memory cell and reference cell may become different from each other in the data readout operation, thereby causing the sense amplifier to erroneously operate.
Conventionally, in order to make the characteristics of the memory cell and reference cell equal to each other, the control gates of the memory cell and reference cell may be commonly connected to receive the same power source voltage SW. However, in this case, programming voltage Vpp is supplied to the control gate of the reference cell when data is programmed into the memory cell. In the ordinary operation, no electron is injected into the floating gate of the reference cell, but in this case, electrons may be injected into the floating gate by the high voltage stress due to application of voltage Vpp to the control gate thereof although it is small in amount. Accordingly, when the memory device is used over a long period of time, the operation characteristic of the reference cell may be changed. Further, with this method, each time a new one of the memory cells is selected, a corresponding one of the reference cells is selected, and therefore the reference potential may be changed depending on the selection of reference cell.
As described above, in the conventional semiconductor memory device, the gate of the reference cell is connected to directly receive the readout power source voltage and therefore there is a possibility that the sense amplifier may be erroneously operated by the influence of noise. Further, in the prior art, if the same voltage is supplied from the same power source to the control gates of the memory cell and reference cell in order to set the characteristics of the memory cell and reference cell equal to each other, the characteristic of the reference cell may be changed, or the reference potential may be changed when a new memory cell is selected, thus lowering the reliability thereof.